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[AArch64][CodeGen] Allow vectors larger than hardware support to use SVE's load zero...
authorDinar Temirbulatov <dinar.temirbulatov@arm.com>
Wed, 19 Apr 2023 14:17:32 +0000 (14:17 +0000)
committerDinar Temirbulatov <dinar.temirbulatov@arm.com>
Wed, 19 Apr 2023 14:17:32 +0000 (14:17 +0000)
commit3e76d012d174a2e33564a6d8476c7f88c7d1b4b8
tree4dabdf0006d82aba67104fe013bf175d60570653tree | snapshot
parent04452e83ded9bfca0ff272fae9c537dde028daf2commit | diff
[AArch64][CodeGen] Allow vectors larger than hardware support to use SVE's load zero/sign-extend for fixed vectors.

Prefer to fold LOAD + SIGN/ZEROEXTEND to SVE load and sign extend instructions
for fixed-length-vectors even if a type is not representable on a hardware.

Differential Revision: https://reviews.llvm.org/D147533
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp diff | blob | history
llvm/test/CodeGen/AArch64/sve-fixed-length-ext-loads.ll diff | blob | history
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ext-loads.ll diff | blob | history
Domain: System / Toolchain;