[RISCV] Don't emit fractional VIDs with negative steps
authorFraser Cormack <fraser@codeplay.com>
Tue, 19 Apr 2022 08:25:40 +0000 (09:25 +0100)
committerFraser Cormack <fraser@codeplay.com>
Thu, 21 Apr 2022 06:00:34 +0000 (07:00 +0100)
commit3e678cb77264907fbc2899c291ce23af308073ff
tree1ca7e8912b1037fb1b04e659a0bc04cb8d4c33b0
parent627e21048a2c040d3e353cc4f0eb8f207b6ea61c
[RISCV] Don't emit fractional VIDs with negative steps

We can't shift-right negative numbers to divide them, so avoid emitting
such sequences. Use negative numerators as a proxy for this situation, since
the indices are always non-negative.

An alternative strategy could be to add a compiler flag to emit division
instructions, which would at least allow us to test the VID sequence
matching itself.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D123796
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll