pinctrl: sh-pfc: r8a77990: Fix MOD_SEL bit numbering
authorTakeshi Kihara <takeshi.kihara.df@renesas.com>
Wed, 12 Dec 2018 10:19:34 +0000 (19:19 +0900)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Mon, 21 Jan 2019 12:24:52 +0000 (13:24 +0100)
commit3e3eebeacad79bda8a9664c86c04f5201e86fece
tree0b36f3a26090f734aca54963e69d95aeca824e64
parent7219a4b645208734d45b1d30a4c35b6f09a0e9e6
pinctrl: sh-pfc: r8a77990: Fix MOD_SEL bit numbering

MOD_SEL register bit numbering was different from R-Car E3 SoC and
R-Car H3/M3-[WN] SoCs.

MOD_SEL 1-bit      H3/M3-[WN]  E3
===============    ==========  =====
Set Value = H'0    b'0         b'0
Set Value = H'1    b'1         b'1

MOD_SEL 2-bits     H3/M3-[WN]  E3
===============    ==========  =====
Set Value = H'0    b'00        b'00
Set Value = H'1    b'01        b'10
Set Value = H'2    b'10        b'01
Set Value = H'3    b'11        b'11

MOD_SEL 3-bits     H3/M3-[WN]  E3
===============    ==========  =====
Set Value = H'0    b'000       b'000
Set Value = H'1    b'001       b'100
Set Value = H'2    b'010       b'010
Set Value = H'3    b'011       b'110
Set Value = H'4    b'100       b'001
Set Value = H'5    b'101       b'101
Set Value = H'6    b'110       b'011
Set Value = H'7    b'111       b'111

This patch replaces the #define name and value of MOD_SEL.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Fixes: 6d4036a1e3b3 ("pinctrl: sh-pfc: Initial R8A77990 PFC support")
[shimoda: Split a patch per SoC and revise the commit log]
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
[geert: Use macros to do the actual reordering]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
drivers/pinctrl/sh-pfc/pfc-r8a77990.c