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(parent: 4fcba55) | patch
clk: sprd: add adjustable pll support
authorChunyan Zhang <chunyan.zhang@spreadtrum.com>
Thu, 7 Dec 2017 12:57:10 +0000 (20:57 +0800)
committerStephen Boyd <sboyd@codeaurora.org>
Thu, 21 Dec 2017 23:00:53 +0000 (15:00 -0800)
commit3e37b005580b9db89d7f335e121d52d3bd58e234
tree49012bb7f11db65920d47855a3a29cd8fac8ab9atree | snapshot
parent4fcba55cc621795caee6ba3503dbe70d10e268b2commit | diff
clk: sprd: add adjustable pll support

Introduced a common adjustable pll clock driver for Spreadtrum SoCs.

Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/sprd/Makefile diff | blob | history
drivers/clk/sprd/pll.c [new file with mode: 0644] blob
drivers/clk/sprd/pll.h [new file with mode: 0644] blob
Domain: System / Kernel;