[dump] Remove NDEBUG from test to enable dump methods [NFC]
authorDon Hinton <hintonda@gmail.com>
Thu, 12 Oct 2017 16:16:06 +0000 (16:16 +0000)
committerDon Hinton <hintonda@gmail.com>
Thu, 12 Oct 2017 16:16:06 +0000 (16:16 +0000)
commit3e0199f7ebab06654168e72add49b7f8eed75b27
treec50690f9c8f9ff646b035e30b5840f36c5b169eb
parent3a72909b7ed7ba81fab3e7a0ed3bfb98ee070418
[dump] Remove NDEBUG from test to enable dump methods [NFC]

Summary:
Add LLVM_FORCE_ENABLE_DUMP cmake option, and use it along with
LLVM_ENABLE_ASSERTIONS to set LLVM_ENABLE_DUMP.

Remove NDEBUG and only use LLVM_ENABLE_DUMP to enable dump methods.

Move definition of LLVM_ENABLE_DUMP from config.h to llvm-config.h so
it'll be picked up by public headers.

Differential Revision: https://reviews.llvm.org/D38406

llvm-svn: 315590
113 files changed:
llvm/CMakeLists.txt
llvm/bindings/ocaml/llvm/llvm_ocaml.c
llvm/include/llvm/Analysis/DominanceFrontier.h
llvm/include/llvm/Analysis/DominanceFrontierImpl.h
llvm/include/llvm/Analysis/RegionInfo.h
llvm/include/llvm/Analysis/RegionInfoImpl.h
llvm/include/llvm/CodeGen/TargetSchedule.h
llvm/include/llvm/Config/config.h.cmake
llvm/include/llvm/Config/llvm-config.h.cmake
llvm/include/llvm/IR/Attributes.h
llvm/include/llvm/MC/MCSchedule.h
llvm/include/llvm/Object/Wasm.h
llvm/include/llvm/Support/Compiler.h
llvm/lib/Analysis/AliasSetTracker.cpp
llvm/lib/Analysis/BlockFrequencyInfoImpl.cpp
llvm/lib/Analysis/CallGraph.cpp
llvm/lib/Analysis/DependenceAnalysis.cpp
llvm/lib/Analysis/DominanceFrontier.cpp
llvm/lib/Analysis/IVUsers.cpp
llvm/lib/Analysis/InlineCost.cpp
llvm/lib/Analysis/LazyCallGraph.cpp
llvm/lib/Analysis/LoopInfo.cpp
llvm/lib/Analysis/MemorySSA.cpp
llvm/lib/Analysis/PHITransAddr.cpp
llvm/lib/Analysis/RegionInfo.cpp
llvm/lib/Analysis/ScalarEvolution.cpp
llvm/lib/Analysis/Trace.cpp
llvm/lib/Bitcode/Writer/ValueEnumerator.cpp
llvm/lib/CodeGen/AsmPrinter/DIE.cpp
llvm/lib/CodeGen/AsmPrinter/DebugLocEntry.h
llvm/lib/CodeGen/BranchRelaxation.cpp
llvm/lib/CodeGen/CodeGenPrepare.cpp
llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
llvm/lib/CodeGen/GlobalISel/RegisterBank.cpp
llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
llvm/lib/CodeGen/InlineSpiller.cpp
llvm/lib/CodeGen/LexicalScopes.cpp
llvm/lib/CodeGen/LiveDebugValues.cpp
llvm/lib/CodeGen/LiveDebugVariables.cpp
llvm/lib/CodeGen/LiveInterval.cpp
llvm/lib/CodeGen/LiveIntervalAnalysis.cpp
llvm/lib/CodeGen/LivePhysRegs.cpp
llvm/lib/CodeGen/LiveVariables.cpp
llvm/lib/CodeGen/MachineBasicBlock.cpp
llvm/lib/CodeGen/MachineFrameInfo.cpp
llvm/lib/CodeGen/MachineFunction.cpp
llvm/lib/CodeGen/MachineInstr.cpp
llvm/lib/CodeGen/MachineLoopInfo.cpp
llvm/lib/CodeGen/MachinePipeliner.cpp
llvm/lib/CodeGen/MachineRegionInfo.cpp
llvm/lib/CodeGen/MachineRegisterInfo.cpp
llvm/lib/CodeGen/MachineScheduler.cpp
llvm/lib/CodeGen/PostRASchedulerList.cpp
llvm/lib/CodeGen/RegAllocPBQP.cpp
llvm/lib/CodeGen/RegisterPressure.cpp
llvm/lib/CodeGen/SafeStackColoring.cpp
llvm/lib/CodeGen/ScheduleDAG.cpp
llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
llvm/lib/CodeGen/ScoreboardHazardRecognizer.cpp
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
llvm/lib/CodeGen/SlotIndexes.cpp
llvm/lib/CodeGen/SplitKit.cpp
llvm/lib/CodeGen/StackColoring.cpp
llvm/lib/CodeGen/TargetRegisterInfo.cpp
llvm/lib/CodeGen/VirtRegMap.cpp
llvm/lib/IR/AsmWriter.cpp
llvm/lib/IR/Attributes.cpp
llvm/lib/IR/ConstantRange.cpp
llvm/lib/IR/Core.cpp
llvm/lib/IR/DebugLoc.cpp
llvm/lib/IR/GCOV.cpp
llvm/lib/IR/Pass.cpp
llvm/lib/IR/ValueSymbolTable.cpp
llvm/lib/MC/MCExpr.cpp
llvm/lib/MC/MCFragment.cpp
llvm/lib/MC/MCInst.cpp
llvm/lib/MC/MCLabel.cpp
llvm/lib/MC/MCParser/MCAsmParser.cpp
llvm/lib/MC/MCSection.cpp
llvm/lib/MC/MCSymbol.cpp
llvm/lib/MC/MCValue.cpp
llvm/lib/MC/SubtargetFeature.cpp
llvm/lib/MC/WasmObjectWriter.cpp
llvm/lib/Option/Arg.cpp
llvm/lib/Option/ArgList.cpp
llvm/lib/Option/Option.cpp
llvm/lib/ProfileData/SampleProf.cpp
llvm/lib/Support/APFloat.cpp
llvm/lib/Support/APInt.cpp
llvm/lib/Support/BranchProbability.cpp
llvm/lib/Support/Twine.cpp
llvm/lib/TableGen/Record.cpp
llvm/lib/TableGen/TGParser.cpp
llvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp
llvm/lib/Target/AMDGPU/GCNIterativeScheduler.cpp
llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
llvm/lib/Target/ARM/ARMConstantPoolValue.cpp
llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
llvm/lib/Target/Mips/MipsConstantIslandPass.cpp
llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
llvm/lib/Target/X86/X86FloatingPoint.cpp
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
llvm/lib/Transforms/Coroutines/CoroFrame.cpp
llvm/lib/Transforms/Scalar/GVN.cpp
llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
llvm/lib/Transforms/Scalar/SROA.cpp
llvm/utils/TableGen/AsmMatcherEmitter.cpp
llvm/utils/TableGen/SubtargetEmitter.cpp
llvm/utils/TableGen/SubtargetFeatureInfo.cpp