Fix an issue of pseudo atomic instruction DAG schedule
authorMichael Liao <michael.liao@intel.com>
Tue, 22 Jan 2013 21:47:38 +0000 (21:47 +0000)
committerMichael Liao <michael.liao@intel.com>
Tue, 22 Jan 2013 21:47:38 +0000 (21:47 +0000)
commit3dffc5e2b73a67dc6ca4feb686fb618c749b002c
tree3be0e6bb3fcd422c7cbcb9123b842b59a2a12277
parent81c944cadb7f9e55b3517b7423a820e2577b9279
Fix an issue of pseudo atomic instruction DAG schedule

- Add list of physical registers clobbered in pseudo atomic insts
  Physical registers are clobbered when pseudo atomic instructions are
  expanded. Add them in clobber list to prevent DAG scheduler to
  mis-schedule them after these insns are declared side-effect free.
- Add test case from Michael Kuperstein <michael.m.kuperstein@intel.com>

llvm-svn: 173200
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/lib/Target/X86/X86InstrCompiler.td
llvm/test/CodeGen/X86/atomic-dagsched.ll [new file with mode: 0644]