AArch64: Combine cmeq 0 + not into cmtst
authorTamar Christina <tamar.christina@arm.com>
Wed, 20 Oct 2021 16:11:52 +0000 (17:11 +0100)
committerTamar Christina <tamar.christina@arm.com>
Wed, 20 Oct 2021 16:11:52 +0000 (17:11 +0100)
commit3db4440d4c79f0a21c6574482c85bbd44a9fd8a6
treeafb2297f3904fd0894910602ad6b3c8cd757bc8d
parent52da40ffe2aaf086f622e513cc99a64bc7573a67
AArch64: Combine cmeq 0 + not into cmtst

This turns a bitwise inverse of an equality comparison with 0 into a compare of
bitwise nonzero (cmtst).

We already have one pattern for cmsts, this adds an additional one which does
not require an additional bitwise and.

i.e.

#include <arm_neon.h>

uint8x8_t bar(int16x8_t abs_row0, int16x8_t row0) {
  uint16x8_t row0_diff =
    vreinterpretq_u16_s16(veorq_s16(abs_row0, vshrq_n_s16(row0, 15)));
  uint8x8_t abs_row0_gt0 =
    vmovn_u16(vcgtq_u16(vreinterpretq_u16_s16(abs_row0), vdupq_n_u16(0)));
  return abs_row0_gt0;
}

now generates:

bar:
        cmtst   v0.8h, v0.8h, v0.8h
        xtn     v0.8b, v0.8h
        ret

instead of:

bar:
        cmeq    v0.8h, v0.8h, #0
        not     v0.16b, v0.16b
        xtn     v0.8b, v0.8h
        ret

gcc/ChangeLog:

* config/aarch64/aarch64-simd.md (*aarch64_cmtst_same_<mode>): New.

gcc/testsuite/ChangeLog:

* gcc.target/aarch64/mvn-cmeq0-1.c: New test.
gcc/config/aarch64/aarch64-simd.md
gcc/testsuite/gcc.target/aarch64/mvn-cmeq0-1.c [new file with mode: 0644]