perf/intel: Remove Perfmon-v4 counter_freezing support
authorPeter Zijlstra <peterz@infradead.org>
Tue, 10 Nov 2020 15:37:51 +0000 (16:37 +0100)
committerPeter Zijlstra <peterz@infradead.org>
Wed, 27 Jan 2021 16:26:58 +0000 (17:26 +0100)
commit3daa96d67274653b7c461b30ef9581d68e905fe1
treebcf57dc2211d2ecff9a9013e455d6bd2f8da8cd5
parentabd562df94d19d0a9769971a35801b3f4991715d
perf/intel: Remove Perfmon-v4 counter_freezing support

Perfmon-v4 counter freezing is fundamentally broken; remove this default
disabled code to make sure nobody uses it.

The feature is called Freeze-on-PMI in the SDM, and if it would do that,
there wouldn't actually be a problem, *however* it does something subtly
different. It globally disables the whole PMU when it raises the PMI,
not when the PMI hits.

This means there's a window between the PMI getting raised and the PMI
actually getting served where we loose events and this violates the
perf counter independence. That is, a counting event should not result
in a different event count when there is a sampling event co-scheduled.

This is known to break existing software (RR).

Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Documentation/admin-guide/kernel-parameters.txt
arch/x86/events/intel/core.c
arch/x86/events/perf_event.h