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(parent: 8db89b2) | patch
drm/amd/display: Programming correct VRR_EN bit in VTEM structure
authorHugo Hu <hugo.hu@amd.com>
Wed, 27 Feb 2019 07:18:08 +0000 (15:18 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 21 Mar 2019 04:39:48 +0000 (23:39 -0500)
commit3d5cc272319d6b7bf2e7d8aa9b1c3b0fe3e85b3f
treeef40d2d2d0b87f354b588b236d0ae8bfff142ec7tree | snapshot
parent8db89b2e39ffe363f27fdd335e35b59c90979ea5commit | diff
drm/amd/display: Programming correct VRR_EN bit in VTEM structure

[Why]
In HDMI plugfest, MTK report our EMP with VRR_EN bit = 0.
VRR_EN bit is EMP-MD0-bit 0. Currently driver set 1 to bit 3.

[How]
Programming correct VRR_EN bit in EMP-MD0-bit0.

Signed-off-by: Hugo Hu <hugo.hu@amd.com>
Reviewed-by: Reza Amini <Reza.Amini@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/modules/freesync/freesync.c diff | blob | history
Domain: System / Kernel;