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(parent: 2577c2b) | patch
clk:starfive:Change PLL0 rate to 1.5GHz
authorXingyu Wu <xingyu.wu@starfivetech.com>
Wed, 26 Oct 2022 06:56:09 +0000 (14:56 +0800)
committerXingyu Wu <xingyu.wu@starfivetech.com>
Wed, 26 Oct 2022 07:10:21 +0000 (15:10 +0800)
commit3d15b255cdf4091a020b50922f6d348333d9983c
tree36bdaf0b964c65f0c0634ac1ebfdaae62e9e3b97tree | snapshot
parent2577c2b760ff5b7c394ece88e947229803cf9dffcommit | diff
clk:starfive:Change PLL0 rate to 1.5GHz

Change PLL0 rate to 1.5GHz and change cpu_core divider.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
drivers/clk/starfive/clk-starfive-jh7110-gen.c [changed mode: 0755->0644] diff | blob | history
drivers/clk/starfive/clk-starfive-jh7110-pll.h [changed mode: 0755->0644] diff | blob | history
Domain: System / Kernel;