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author	Luis Marques <luismarques@lowrisc.org>
	Tue, 17 Sep 2019 11:15:35 +0000 (11:15 +0000)
committer	Luis Marques <luismarques@lowrisc.org>
	Tue, 17 Sep 2019 11:15:35 +0000 (11:15 +0000)
commit	3d0fbafd0bce43bb9106230a45d1130f7a40e5ec
tree	e71d5a01eeebf585596a126cd834fddab0c2c784	tree \| snapshot
parent	3ab9e8b81858cdcf4f381b4238315cb1d434e984	commit \| diff

[RISCV] Switch to the Machine Scheduler

Most of the test changes are trivial instruction reorderings and differing
register allocations, without any obvious performance impact.

Differential Revision: https://reviews.llvm.org/D66973

llvm-svn: 372106

73 files changed:

llvm/lib/Target/RISCV/RISCVSubtarget.h		diff \| blob \| history
llvm/test/CodeGen/RISCV/add-before-shl.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/addc-adde-sube-subc.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/addcarry.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/alloca.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/alu64.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/arith-with-overflow.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/atomic-cmpxchg-flag.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/atomic-rmw.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/bare-select.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/blockaddress.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/callee-saved-gprs.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/calling-conv-ilp32.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/calling-conv-lp64.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/codemodel-lowering.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/compress.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/div.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/double-arith.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/double-br-fcmp.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/double-calling-conv.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/double-convert.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/double-fcmp.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/double-imm.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/double-intrinsics.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/double-mem.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/double-previous-failure.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/double-select-fcmp.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/float-arith.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/float-br-fcmp.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/float-convert.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/float-fcmp.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/float-imm.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/float-intrinsics.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/float-mem.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/float-select-fcmp.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/fp128.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/frame-info.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/get-setcc-result-type.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/imm-cse.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/imm.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/indirectbr.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/legalize-fneg.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/lsr-legaladdimm.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/mem.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/mem64.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/mul.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/remat.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rv64f-float-convert.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rv64i-complex-float.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rv64i-w-insts-legalization.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/select-optimize-multiple.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/setcc-logic.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/shifts.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/split-offsets.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/vararg.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll		diff \| blob \| history

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