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(parent: 47e01e7) | patch
radv: adjust ESGS ring buffer size computation on VI+
authorSamuel Pitoiset <samuel.pitoiset@gmail.com>
Mon, 10 Sep 2018 16:14:41 +0000 (18:14 +0200)
committerSamuel Pitoiset <samuel.pitoiset@gmail.com>
Tue, 11 Sep 2018 09:30:19 +0000 (11:30 +0200)
commit3d08631fe5779cfadfeba3df89fbbddf3fde331b
tree31fccd2751c2f3925826a59ffc4b7e88fdc30fd4tree | snapshot
parent47e01e77d8b658606527f048cda786440f7fbe85commit | diff
radv: adjust ESGS ring buffer size computation on VI+

Noticed while working in this area. Ported from RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
src/amd/vulkan/radv_pipeline.c diff | blob | history
Domain: Graphics System / GL;