clk: renesas: Add support for setting MMCIF clock divider on Gen2
authorMarek Vasut <marek.vasut+renesas@gmail.com>
Mon, 18 Mar 2019 05:04:02 +0000 (06:04 +0100)
committerMarek Vasut <marex@denx.de>
Mon, 25 Mar 2019 19:26:53 +0000 (20:26 +0100)
commit3cb2849c76ddb7b4da6a164b8513e1309715d765
treea0d5034ca91c895a78f9ae0eef4f04c8ed4e2774
parent4b135d54649eb79d5dfcd20feee82f6675c502c3
clk: renesas: Add support for setting MMCIF clock divider on Gen2

Add code for configuring the MMC0CKCR/MMC1CKCR on Gen2 platforms.
This allows the MMCIF driver to set higher clock rate if desired.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
drivers/clk/renesas/clk-rcar-gen2.c