mpc83xx: don't set SICRH_TSOBI1 to RMII/RTBI operation
authorKim Phillips <kim.phillips@freescale.com>
Fri, 5 Jun 2009 19:11:33 +0000 (14:11 -0500)
committerKim Phillips <kim.phillips@freescale.com>
Mon, 8 Jun 2009 15:45:09 +0000 (10:45 -0500)
commit3c9b1ee17e19bd6d80344678d41a85e52b0be713
treea319178aa16dbe1e083a6ff2b99c5cd71207c18d
parent3bc8556f9b24af60dba2b55a0abb1182dff45ecc
mpc83xx: don't set SICRH_TSOBI1 to RMII/RTBI operation

In GMII mode (which operates at 3.3V) both SICRH TSEC1/2 output buffer
impedance bits should be clear, i.e., SICRH[TSIOB1] = 0 and SICRH[TSIOB2] = 0.
SICRH[TSIOB1] was erroneously being set high.

U-Boot always operated this PHY interface in GMII mode.  It is assumed this
was missed in the clean up by the original board porters, and copied along
to the TQM and sbc boards.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Acked-by: Ira Snyder <iws@ovro.caltech.edu>
Reviewed-by: David Hawkins <dwh@ovro.caltech.edu>
Tested-by: Paul Gortmaker <paul.gortmaker@windriver.com>
CC: Dave Liu <DaveLiu@freescale.com>
include/configs/MPC8349EMDS.h
include/configs/TQM834x.h
include/configs/sbc8349.h