[AArch64] Fix sched model for tsv110

[AArch64] Fix sched model for tsv110

Update three changes:
1.Split the Load/Store resources into two, Ld0St and Ld1,
  since only one of them is capable of stores.
2.Integer ADD and SUB instructions have different latencies
  and processor resource usage (pipeline) when they have a shift of
  zero vs. non-zero, refer to D8043
3.The throughout of scalar DIV instruction.

Reviewed By: dmgreen, bryanpkc

Differential Revision: https://reviews.llvm.org/D132529