projects / platform / upstream / mesa.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 8750f43) | patch
intel/perf: switch query code to use query layout
authorLionel Landwerlin <lionel.g.landwerlin@intel.com>
Wed, 26 Aug 2020 09:41:41 +0000 (12:41 +0300)
committerMarge Bot <eric+marge@anholt.net>
Tue, 2 Feb 2021 13:25:54 +0000 (13:25 +0000)
commit3c513250255d6ad031b8574ed7bb54a1e1ccdeef
treed46a8cb834f3e67599152859b81f5ee093e19bfatree | snapshot
parent8750f43a9077b3b53f54505aaa2cc46fab5d4f90commit | diff
intel/perf: switch query code to use query layout

That way we can describe new registers to that could be used both by
Anv & Iris/i965 without having to modifying code in multiple places.

v2: Do reverse order for begin queries so that we have MI_RPC as close
    as possible from the drawcall

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6518>
src/intel/perf/gen_perf_query.c diff | blob | history
Domain: Graphics System / GL;