[X86][Costmodel] Load/store i32/f32 Stride=4 VF=4 interleaving costs
authorRoman Lebedev <lebedev.ri@gmail.com>
Mon, 4 Oct 2021 16:30:07 +0000 (19:30 +0300)
committerRoman Lebedev <lebedev.ri@gmail.com>
Tue, 5 Oct 2021 13:58:57 +0000 (16:58 +0300)
commit3c2e22b795485df28ca898bd3a58b6478c1e903d
tree0932ddf8b6952f035589b70bf0b544ff8dec3e38
parentb6234c1edffc8286815c61887eb02fd6ddab0090
[X86][Costmodel] Load/store i32/f32 Stride=4 VF=4 interleaving costs

The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3

For load we have:
https://godbolt.org/z/avq1oz98W - for intels `Block RThroughput: =8.0`; for ryzens, `Block RThroughput: =4.0`
So could pick cost of `8`.

For store we have:
https://godbolt.org/z/89PGMc1qs - for intels `Block RThroughput: =6.0`; for ryzens, `Block RThroughput: <=6.0`
So we could pick cost of `6`.

I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D111061
llvm/lib/Target/X86/X86TargetTransformInfo.cpp
llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-4.ll
llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-4.ll
llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-4.ll
llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-4.ll