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drm/tegra: dpaux: Fix transfers larger than 4 bytes
authorThierry Reding <treding@nvidia.com>
Thu, 11 Jun 2015 16:33:48 +0000 (18:33 +0200)
committerThierry Reding <treding@nvidia.com>
Fri, 12 Jun 2015 14:22:46 +0000 (16:22 +0200)
commit3c1dae0a07c651526f8e878d223a88f82caa5a50
treec71bc338728059b18bfd0f031956fbb73e288751tree | snapshot
parentb787f68c36d49bb1d9236f403813641efa74a031commit | diff
drm/tegra: dpaux: Fix transfers larger than 4 bytes

The DPAUX read/write FIFO registers aren't sequential in the register
space, causing transfers larger than 4 bytes to cause accesses to non-
existing FIFO registers.

Fixes: 6b6b604215c6 ("drm/tegra: Add eDP support")
Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/gpu/drm/tegra/dpaux.c diff | blob | history
Domain: System / Kernel;