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(parent: ecaab10) | patch
[AArch64] Combine to UMULL if top bits are known zero
authorDavid Green <david.green@arm.com>
Tue, 20 Dec 2022 13:50:34 +0000 (13:50 +0000)
committerDavid Green <david.green@arm.com>
Tue, 20 Dec 2022 13:50:34 +0000 (13:50 +0000)
commit3c0c24e0c1d37e903eab484b34ef854ec785346b
treefb9ff8c922af75eb21b68944309e4b2074a87f8atree | snapshot
parentecaab107e4d0a21282cb838b0b505cdea9f87e56commit | diff
[AArch64] Combine to UMULL if top bits are known zero

Given mul(zext(a), b), we can convert to a umull so long as we know that
the top bits of b are zero. This uses MaskedValueIsZero to detect that
case for NEON UMULL patterns.

Differential Revision: https://reviews.llvm.org/D140287
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp diff | blob | history
llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll diff | blob | history
llvm/test/CodeGen/AArch64/aarch64-smull.ll diff | blob | history
Domain: System / Toolchain;