drm/i915: Update gen12 multicast register ranges
authorMatt Roper <matthew.d.roper@intel.com>
Fri, 9 Oct 2020 19:44:42 +0000 (12:44 -0700)
committerMatt Roper <matthew.d.roper@intel.com>
Sat, 10 Oct 2020 01:54:44 +0000 (18:54 -0700)
commit3bcacad3d7a9ab727e9ac1a110dac4ddc78bca32
tree7abc93e719e3e9db622fea5e724e9a7c84d87eed
parent92f5df0d448bb0951c49f4981405a32ffaa2545d
drm/i915: Update gen12 multicast register ranges

The updated bspec forcewake table also provides us with new multicast
ranges that should be reflected in our workaround code.

Note that there are different types of multicast registers with
different styles of replication and different steering registers.  The
i915 MCR range lists we're updating here are only used to ensure we can
verify workarounds properly (i.e., if we can't steer register reads we
don't want to verify workarounds where an unsteered read might hit a
fused-off instance of the unit).  Because of this, we don't need to
include any of the multicast ranges where all instances of the register
will always present and fusing doesn't play a role.  Specifically, that
means that we are not including the MCR ranges designated as "SQIDI" in
the bspec.

Bspec: 66696
Cc: Caz Yokoyama <caz.yokoyama@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201009194442.3668677-4-matthew.d.roper@intel.com
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
drivers/gpu/drm/i915/gt/intel_workarounds.c