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(parent: aed39a3) | patch
aarch64: Add vector implementations of sin routines
authorJoe Ramsay <Joe.Ramsay@arm.com>
Wed, 28 Jun 2023 11:19:37 +0000 (12:19 +0100)
committerSzabolcs Nagy <szabolcs.nagy@arm.com>
Fri, 30 Jun 2023 08:04:16 +0000 (09:04 +0100)
commit3bb1af20513b8b70b8d404c71fb0956f00f8bf6b
tree1043f476abc9d2587a2d2ee8f1dabd06b104162atree | snapshot
parentaed39a3aa3ea68b14dce3395fb14b1416541e6c6commit | diff
aarch64: Add vector implementations of sin routines

Optimised implementations for single and double precision, Advanced
SIMD and SVE, copied from Arm Optimized Routines.

As previously, data tables are used via a barrier to prevent
overly aggressive constant inlining. Special-case handlers are
marked NOINLINE to avoid incurring the penalty of switching call
standards unnecessarily.

Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
13 files changed:
sysdeps/aarch64/fpu/Makefile diff | blob | history
sysdeps/aarch64/fpu/Versions diff | blob | history
sysdeps/aarch64/fpu/bits/math-vector.h diff | blob | history
sysdeps/aarch64/fpu/sin_advsimd.c [new file with mode: 0644] blob
sysdeps/aarch64/fpu/sin_sve.c [new file with mode: 0644] blob
sysdeps/aarch64/fpu/sinf_advsimd.c [new file with mode: 0644] blob
sysdeps/aarch64/fpu/sinf_sve.c [new file with mode: 0644] blob
sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c diff | blob | history
sysdeps/aarch64/fpu/test-double-sve-wrappers.c diff | blob | history
sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c diff | blob | history
sysdeps/aarch64/fpu/test-float-sve-wrappers.c diff | blob | history
sysdeps/aarch64/libm-test-ulps diff | blob | history
sysdeps/unix/sysv/linux/aarch64/libmvec.abilist diff | blob | history
Domain: System / Toolchain;