Gfx-Display: correct the reg setting of MIPIA_PORT_CTRL in driver

Gfx-Display: correct the reg setting of MIPIA_PORT_CTRL in driver

BZ: 29163

This patch corrects the reg setting of bit 23 in MIPIA_PORT_CTRL. This bit should
be always set to 0 for PNWB0 and forward. The bit defination changed from PNW A0
to B0, but the Spec is not updated to the date. Here in driver correct this bit setting
to 0 as required.

Change-Id: I7bef71ccdeedd349a35259b78c1aab1fca0f3371
Signed-off-by: Lei Zhang <lei.zhang@intel.com>
Reviewed-on: http://android.intel.com:8080/40888
Reviewed-by: Xu, Randy <randy.xu@intel.com>
Tested-by: Xu, Randy <randy.xu@intel.com>
Reviewed-by: Ai, Ke <ke.ai@intel.com>
Reviewed-by: buildbot <buildbot@intel.com>
Tested-by: buildbot <buildbot@intel.com>