RISC-V: Create unique identification for SoC PMU

RISC-V: Create unique identification for SoC PMU

The SBI PMU platform driver did not provide any identification for
perf events matching. This patch introduces a new sysfs file inside the
platform device (soc:pmu/id) for pmu identification.

The identification is a 64-bit value generated as:
[63-32]: mvendorid;
[31]: marchid[MSB];
[30-16]: marchid[15-0];
[15-0]: mimpid[15MSBs];

The CSRs are detailed in the RISC-V privileged spec [1].
The marchid is split in MSB + 15LSBs, due to the MSB being used for
open-source architecture identification.

[1] https://github.com/riscv/riscv-isa-manual

Signed-off-by: João Mário Domingos <joao.mario@tecnico.ulisboa.pt>