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(parent: 7bf168c) | patch
drm/msm/dsi: fix check-before-set in the 7nm dsi_pll code
authorDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Wed, 24 Feb 2021 22:47:51 +0000 (01:47 +0300)
committerRob Clark <robdclark@chromium.org>
Wed, 17 Mar 2021 16:14:47 +0000 (09:14 -0700)
commit3b24cdfc721a5f1098da22f9f68ff5f4a5efccc9
tree4009b3cbba09a42810a473f363d068f822a72a7ctree | snapshot
parent7bf168c8fe8c6166b5dc10005fe7f250164da0adcommit | diff
drm/msm/dsi: fix check-before-set in the 7nm dsi_pll code

Fix setting min/max DSI PLL rate for the V4.1 7nm DSI PLL (used on
sm8250). Current code checks for pll->type before it is set (as it is
set in the msm_dsi_pll_init() after calling device-specific functions.

Cc: Jonathan Marek <jonathan@marek.ca>
Fixes: 1ef7c99d145c ("drm/msm/dsi: add support for 7nm DSI PHY/PLL")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
drivers/gpu/drm/msm/dsi/pll/dsi_pll.c diff | blob | history
drivers/gpu/drm/msm/dsi/pll/dsi_pll.h diff | blob | history
drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c diff | blob | history
Domain: System / Kernel;