Fix VGPR + offset Scratch offset folding
authorPetar Avramovic <Petar.Avramovic@amd.com>
Wed, 8 Mar 2023 15:42:14 +0000 (16:42 +0100)
committerPetar Avramovic <Petar.Avramovic@amd.com>
Thu, 9 Mar 2023 09:52:44 +0000 (10:52 +0100)
commit3ae310d0ae3452c7384736c7f8542ee3d1e0f4fd
tree2cbfdcef64263ce4319e93268e102c51bece9395
parent5e56d5999914538c8060e4fd9b23ec19650eebce
Fix VGPR + offset Scratch offset folding

Values in VGPR register are treated as unsigned by hardware.

When value in 32-bit VGPR base can be negative calculate offset using
32-bit add instruction, otherwise use vgpr base(unsigned) + offset.
Does not affect case where whole offset comes from VGPR register
(immediate offset is 0).

LoopStrengthReduce.cpp changes offsets to negative and in some
iterations value in VGPR register could be negative.

Differential Revision: https://reviews.llvm.org/D144956
12 files changed:
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-private.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-private.mir
llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.private.ll
llvm/test/CodeGen/AMDGPU/flat-scratch-i8-i16.ll
llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
llvm/test/CodeGen/AMDGPU/flat-scratch.ll
llvm/test/CodeGen/AMDGPU/memory_clause.ll