[mlir][nvvm] Introduce performance tuning directives

[mlir][nvvm] Introduce performance tuning directives

PTX programming models provides some performance tuning directives; see https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#performance-tuning-directives

The downstream compiler namely `ptxas` leverages these information for better register allocation or to handle other resource management that improves the performance.

This revision introduce all the kernel based directives to MLIR's NVVM dialect. The list is below
```
maxnreg			-> 	max register per thread in CTA
maxntid			-> 	max threads per CTA
reqntid			-> 	exact number of threads per CTA
minnctapersm		-> 	min CTA per SM
```

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D136931