rockchip: clk: update dwmmc clock div
authorKever Yang <kever.yang@rock-chips.com>
Thu, 27 Jul 2017 04:54:01 +0000 (12:54 +0800)
committerPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Sun, 13 Aug 2017 15:15:09 +0000 (17:15 +0200)
commit3a94d75d0e2a3b2519de51dfa1f369d976d9cccc
tree97eceee91df5dd3414f899062ec64041bf7257ed
parent95ca100ba740283e00f0b5354be8ccb04b97cbf9
rockchip: clk: update dwmmc clock div

dwmmc controller has default internal divider by 2,
and we always provide double of the clock rate request by
dwmmc controller. Sync code for all Rockchip SoC with:
4055b46 rockchip: clk: rk3288: fix mmc clock setting

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[fixup for 'missing DIV_ROUND_UP' conflict for clk_rk3288.c:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
drivers/clk/rockchip/clk_rk3036.c
drivers/clk/rockchip/clk_rk3188.c
drivers/clk/rockchip/clk_rk322x.c
drivers/clk/rockchip/clk_rk3288.c
drivers/clk/rockchip/clk_rk3328.c
drivers/clk/rockchip/clk_rk3399.c