[AArch64] Lower READCYCLECOUNTER using MRS CNTVCT_EL0

[AArch64] Lower READCYCLECOUNTER using MRS CNTVCT_EL0

As suggested in D12425 it would be better for the readcyclecounter
function on ARM architecture to use the CNTVCT_EL0 register
(Counter-timer Virtual Count register) instead of the PMCCNTR_EL0
(Performance Monitors Cycle Count Register) because the PMCCNTR_EL0 is a
PMU register which, depending on the configuration, it might always
return zeroes and it doesn't guaranteed to always be increased.

Differential Revision: https://reviews.llvm.org/D136999