x86/Intel: disassemble vcvt{,u}si2s{d,s} with correct operand order
authorJan Beulich <jbeulich@novell.com>
Mon, 1 Jun 2015 07:51:28 +0000 (09:51 +0200)
committerJan Beulich <jbeulich@suse.com>
Mon, 1 Jun 2015 07:51:28 +0000 (09:51 +0200)
commit3a8547d2fb5319890dda877fb313822053083c3a
tree8c715e8520fd5e5f0cfb29e8596a4afb2b821e8e
parent015c54d5a6a052f074fab168bc70296131276e80
x86/Intel: disassemble vcvt{,u}si2s{d,s} with correct operand order

As pointed out before, the documentation mandates the rounding mode to
follow the GPR, so disassembler should produce output accordingly.

gas/testsuite/
2015-06-01  Jan Beulich  <jbeulich@suse.com>

* gas/i386/avx512f.s: Adjust operand order for Intel syntax
vcvt{,u}si2ss.
* gas/i386/x86-64-avx512f.s: Adjust operand order for Intel
syntax vcvt{,u}si2s{d,s}.

opcodes/
2015-06-01  Jan Beulich  <jbeulich@suse.com>

* i386-dis.c (print_insn): Swap rounding mode specifier and
general purpose register in Intel mode.
gas/testsuite/ChangeLog
gas/testsuite/gas/i386/avx512f-intel.d
gas/testsuite/gas/i386/evex-lig256-intel.d
gas/testsuite/gas/i386/evex-lig512-intel.d
gas/testsuite/gas/i386/x86-64-avx512f-intel.d
gas/testsuite/gas/i386/x86-64-evex-lig256-intel.d
gas/testsuite/gas/i386/x86-64-evex-lig512-intel.d
opcodes/ChangeLog
opcodes/i386-dis.c