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(parent: e8716a6) | patch
[ARM] Disable VLD4 under MVE
authorDavid Green <david.green@arm.com>
Sun, 8 Dec 2019 09:58:03 +0000 (09:58 +0000)
committerDavid Green <david.green@arm.com>
Sun, 8 Dec 2019 10:37:29 +0000 (10:37 +0000)
commit3a6eb5f16054e8c0f41a37542a5fc806016502a0
treef46645123431bee65ab83f055038064fdbd6e9cbtree | snapshot
parente8716a6df7abad68b6cf81c437a2e0524e88f3adcommit | diff
[ARM] Disable VLD4 under MVE

Alas, using half the available vector registers in a single instruction
is just too much for the register allocator to handle. The mve-vldst4.ll
test here fails when these instructions are enabled at present. This
patch disables the generation of VLD4 and VST4 by adding a
mve-max-interleave-factor option, which we currently default to 2.

Differential Revision: https://reviews.llvm.org/D71109
llvm/lib/Target/ARM/ARMISelLowering.cpp diff | blob | history
llvm/test/CodeGen/Thumb2/mve-vld4.ll diff | blob | history
llvm/test/CodeGen/Thumb2/mve-vldst4.ll [new file with mode: 0644] blob
llvm/test/CodeGen/Thumb2/mve-vst4.ll diff | blob | history
llvm/test/Transforms/InterleavedAccess/ARM/interleaved-accesses.ll diff | blob | history
llvm/test/Transforms/LoopVectorize/ARM/mve-interleaved-cost.ll diff | blob | history
llvm/test/Transforms/LoopVectorize/ARM/mve-vldn.ll [new file with mode: 0644] blob
Domain: System / Toolchain;