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(parent: 159b6d3) | patch
dt-bingings:uart:jh7110: add clks and reset signals to uarts
authoryanhong.wang <yanhong.wang@starfivetech.com>
Tue, 19 Apr 2022 07:54:56 +0000 (15:54 +0800)
committeryanhong.wang <yanhong.wang@starfivetech.com>
Sun, 24 Apr 2022 02:22:50 +0000 (10:22 +0800)
commit3a5b1998599af0477dc9137be2fad96f90a996d1
treeda89d6752d5eb658f5df96f0dcb1f7667217020ftree | snapshot
parent159b6d3671106a6ee99c9acfcd8e64799a4b509ecommit | diff
dt-bingings:uart:jh7110: add clks and reset signals to uarts

Uart uses the clock and reset framework API.

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
arch/riscv/boot/dts/starfive/jh7110.dtsi diff | blob | history
arch/riscv/boot/dts/starfive/jh7110_clk.dtsi [changed mode: 0755->0644] diff | blob | history
Domain: System / Kernel;