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[RISCV] Omit SRA in case of setlt or setge with zero constant
authorElena Lepilkina <elena.lepilkina@syntacore.com>
Wed, 14 Dec 2022 15:37:44 +0000 (18:37 +0300)
committerAnton Afanasyev <anton.afanasyev@syntacore.com>
Wed, 21 Dec 2022 11:19:49 +0000 (14:19 +0300)
commit3a3f725a3cdc44cacb8f9847404a148ee056c913
tree56710a1c4fd1fc5a1304469fb235648d379151dctree | snapshot
parentea21fa3a5977e769a8ba8e7fb7e867dad9306efacommit | diff
[RISCV] Omit SRA in case of setlt or setge with zero constant

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D140206
llvm/lib/Target/RISCV/RISCVISelLowering.cpp diff | blob | history
llvm/test/CodeGen/RISCV/branch_zero.ll diff | blob | history
Domain: System / Toolchain;