AMDGPU: Try to eliminate clearing of high bits of 16-bit instructions
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Tue, 15 Jun 2021 22:51:06 +0000 (18:51 -0400)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Tue, 22 Jun 2021 17:42:49 +0000 (13:42 -0400)
commit39f8a792f0ac4efed11ac906ba76137fc0c9f6a8
treef7c6afb259756716ae394997b2bb2418e7d2fcf3
parent317e92a3e82f88f111e04132195d9daa6b97f1ab
AMDGPU: Try to eliminate clearing of high bits of 16-bit instructions

These used to consistently be zeroed pre-gfx9, but gfx9 made the
situation complicated since now some still do and some don't. This
also manages to pick up a few cases that the pattern fails to optimize
away.

We handle some cases with instruction patterns, but some get
through. In particular this improves the integer cases.
19 files changed:
llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
llvm/lib/Target/AMDGPU/GCNSubtarget.h
llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
llvm/test/CodeGen/AMDGPU/fmax3.ll
llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll
llvm/test/CodeGen/AMDGPU/fmin3.ll
llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll
llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
llvm/test/CodeGen/AMDGPU/high-bits-zeroed-16-bit-ops.mir
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.f16.ll
llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll
llvm/test/CodeGen/AMDGPU/preserve-hi16.ll
llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll
llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll
llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll
llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
llvm/test/CodeGen/AMDGPU/uaddsat.ll
llvm/test/CodeGen/AMDGPU/usubsat.ll