[X86] lowerV16I8Shuffle - create v8i16 mask for PACKUS(AND(),AND()) patterns.
authorSimon Pilgrim <llvm-dev@redking.me.uk>
Thu, 26 Mar 2020 19:59:37 +0000 (19:59 +0000)
committerSimon Pilgrim <llvm-dev@redking.me.uk>
Thu, 26 Mar 2020 19:59:57 +0000 (19:59 +0000)
commit39a52a19ed0206e0ebd1530f881f79a1511a2299
tree40b5ada50b8723cac65dfdd0bb975efe9c3704ff
parentf9e71f4d9d39871390da48207d7fd6b116e370dc
[X86] lowerV16I8Shuffle - create v8i16 mask for PACKUS(AND(),AND()) patterns.

We can improve computeKnownBits results by avoiding excess bitcasts.

For this pattern we were doing:

  (v16i8 PACKUS(v8i16 BITCAST(v16i8 AND(V1, MASK)), v8i16 BITCAST(v16i8 AND(V2, MASK))))

By performing the MASK/AND with a v8i16 type and bitcasting V1/V2 directly we can help computeKnownBits see that the mask is clearing the upper bits and allows shuffle combining to peek through later on.

This will be necessary to extend rG9d1721ce3926 to AVX2+ targets in a future patch.
14 files changed:
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/test/CodeGen/X86/avg.ll
llvm/test/CodeGen/X86/masked_store_trunc.ll
llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll
llvm/test/CodeGen/X86/psubus.ll
llvm/test/CodeGen/X86/shuffle-vs-trunc-256.ll
llvm/test/CodeGen/X86/vector-reduce-and-bool.ll
llvm/test/CodeGen/X86/vector-reduce-or-bool.ll
llvm/test/CodeGen/X86/vector-reduce-xor-bool.ll
llvm/test/CodeGen/X86/vector-shuffle-128-v16.ll
llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll
llvm/test/CodeGen/X86/vector-trunc-math.ll
llvm/test/CodeGen/X86/vector-trunc-ssat.ll
llvm/test/CodeGen/X86/vector-trunc.ll