drm/i915/gen11: enable support for headerless msgs
authorDongwon Kim <dongwon.kim@intel.com>
Thu, 25 Apr 2019 05:50:05 +0000 (06:50 +0100)
committerChris Wilson <chris@chris-wilson.co.uk>
Fri, 24 May 2019 09:06:26 +0000 (10:06 +0100)
commit397049a03022702defa65694c23643f96d5fa113
treef72f5657e7f3ca3c159e8889401061032575962e
parent63e8dcdb4f8e596f2a290af4278e0bca3304a1f1
drm/i915/gen11: enable support for headerless msgs

Setting bit5 (headerless msg for preemptible GPGPU context) of SAMPLER_MODE
register to enable support for the headless msgs on gen11. None of existing
use cases will be affected by this as this change makes both types of
message - headerless and w/ header supported at the same time. It also
complies with the new recommendation for the default bit value for the
next gen.

v2: rewrote commit message to include more information
v3: setting the bit in icl_ctx_workarounds_init()

Signed-off-by: Dongwon Kim <dongwon.kim@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190425055005.21790-1-chris@chris-wilson.co.uk
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
drivers/gpu/drm/i915/gt/intel_workarounds.c
drivers/gpu/drm/i915/i915_reg.h