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[AArch64][GlobalISel] Add combine for G_EXTRACT_VECTOR_ELT to allow selection of...
authorAmara Emerson <amara@apple.com>
Tue, 3 Nov 2020 19:17:31 +0000 (11:17 -0800)
committerAmara Emerson <amara@apple.com>
Wed, 4 Nov 2020 01:25:14 +0000 (17:25 -0800)
commit393b55380afcd8681db03dfbdea2f27ff3517d25
tree17033cc5565fdadf255412a7553aa78c414f0148tree | snapshot
parentc298824f9caf407aedeb4958467fb2a18025638dcommit | diff
[AArch64][GlobalISel] Add combine for G_EXTRACT_VECTOR_ELT to allow selection of pairwise FADD.

For the <2 x float> case, instead of adding another combine or legalization to
get it into a <4 x float> form, I'm just adding a GISel specific selection
pattern to cover it.

Differential Revision: https://reviews.llvm.org/D90699
llvm/lib/Target/AArch64/AArch64Combine.td diff | blob | history
llvm/lib/Target/AArch64/AArch64InstrGISel.td diff | blob | history
llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp diff | blob | history
llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-extractvec-faddp.mir [new file with mode: 0644] blob
llvm/test/CodeGen/AArch64/GlobalISel/select-faddp.mir [new file with mode: 0644] blob
Domain: System / Toolchain;