projects / platform / upstream / llvm.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 0319d4a) | patch
[RISCV] Add isel support for scalar STRICT_FADD/FSUB/FMUL/FDIV/FSQRT.
authorCraig Topper <craig.topper@sifive.com>
Tue, 14 Dec 2021 18:35:38 +0000 (10:35 -0800)
committerCraig Topper <craig.topper@sifive.com>
Tue, 14 Dec 2021 18:50:55 +0000 (10:50 -0800)
commit3926893439c419055b43df4f37db354cde3d02c2
tree0e487983818c4d5e70ac1abfe2f425b390225bf7tree | snapshot
parent0319d4a12ee84c0821a66e5b89002b4d60828ec2commit | diff
[RISCV] Add isel support for scalar STRICT_FADD/FSUB/FMUL/FDIV/FSQRT.

Test that STRICT_FMINNUM/FMAXNUM are lowered to libcalls for f32/f64.
The RISC-V instructions don't match the behavior of fmin/fmax libcalls
with respect to SNaN.

Promoting FMINNUM/FMAXNUM for f16 needs more work outside of the
RISC-V backend.

Reviewed By: asb, arcbbb

Differential Revision: https://reviews.llvm.org/D115680
llvm/lib/Target/RISCV/RISCVISelLowering.cpp diff | blob | history
llvm/lib/Target/RISCV/RISCVInstrInfoD.td diff | blob | history
llvm/lib/Target/RISCV/RISCVInstrInfoF.td diff | blob | history
llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td diff | blob | history
llvm/test/CodeGen/RISCV/double-arith-strict.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/float-arith-strict.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/half-arith-strict.ll [new file with mode: 0644] blob
Domain: System / Toolchain;