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author	Ron Lieberman <ron.lieberman@amd.com>
	Thu, 15 Dec 2022 16:54:41 +0000 (10:54 -0600)
committer	Ron Lieberman <ron.lieberman@amd.com>
	Thu, 15 Dec 2022 16:55:18 +0000 (10:55 -0600)
commit	38f1abef860418f85b1011601d20e9d49aa85adb
tree	18173a3a41b415aa5c411750151a908d34cbe9ae	tree \| snapshot
parent	ccb8a4e3f36937a71a526ca4a3fa29895253ee9d	commit \| diff

Revert "[SelectionDAG] Do not second-guess alignment for alloca"

Breaks amdgpu buildbot https://lab.llvm.org/buildbot/#/builders/193
23491

This reverts commit ffedf47d8b793e07317f82f9c2a5f5425ebb71ad.

43 files changed:

llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp		diff \| blob \| history
llvm/test/CodeGen/AArch64/preferred-alignment.ll		diff \| blob \| history
llvm/test/CodeGen/AArch64/seh-finally.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/call-argument-types.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll		diff \| blob \| history
llvm/test/CodeGen/ARM/ssp-data-layout.ll		diff \| blob \| history
llvm/test/CodeGen/BPF/pr57872.ll		diff \| blob \| history
llvm/test/CodeGen/BPF/undef.ll		diff \| blob \| history
llvm/test/CodeGen/Mips/Fast-ISel/fastalloca.ll		diff \| blob \| history
llvm/test/CodeGen/Mips/atomic64.ll		diff \| blob \| history
llvm/test/CodeGen/Mips/cconv/byval.ll		diff \| blob \| history
llvm/test/CodeGen/Mips/cconv/return-struct.ll		diff \| blob \| history
llvm/test/CodeGen/Mips/largeimmprinting.ll		diff \| blob \| history
llvm/test/CodeGen/Mips/o32_cc_byval.ll		diff \| blob \| history
llvm/test/CodeGen/NVPTX/lower-byval-args.ll		diff \| blob \| history
llvm/test/CodeGen/PowerPC/aix-cc-byval.ll		diff \| blob \| history
llvm/test/CodeGen/PowerPC/aix-sret-param.ll		diff \| blob \| history
llvm/test/CodeGen/PowerPC/byval.ll		diff \| blob \| history
llvm/test/CodeGen/PowerPC/structsinregs.ll		diff \| blob \| history
llvm/test/CodeGen/PowerPC/varargs-struct-float.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/frame.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/mem64.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/vararg.ll		diff \| blob \| history
llvm/test/CodeGen/Thumb2/mve-stack.ll		diff \| blob \| history
llvm/test/CodeGen/VE/Scalar/atomic_cmp_swap.ll		diff \| blob \| history
llvm/test/CodeGen/VE/Scalar/atomic_load.ll		diff \| blob \| history
llvm/test/CodeGen/VE/Scalar/atomic_swap.ll		diff \| blob \| history
llvm/test/CodeGen/WebAssembly/PR40172.ll		diff \| blob \| history
llvm/test/CodeGen/X86/dbg-changes-codegen-branch-folding.ll		diff \| blob \| history
llvm/test/CodeGen/X86/fast-isel-call.ll		diff \| blob \| history
llvm/test/CodeGen/X86/load-local-v3i129.ll		diff \| blob \| history
llvm/test/CodeGen/X86/pr44140.ll		diff \| blob \| history
llvm/test/CodeGen/X86/ssp-data-layout.ll		diff \| blob \| history
llvm/test/CodeGen/X86/win-cleanuppad.ll		diff \| blob \| history
llvm/test/CodeGen/X86/x86-mixed-alignment-dagcombine.ll		diff \| blob \| history
llvm/test/DebugInfo/AArch64/frameindices.ll		diff \| blob \| history
llvm/test/DebugInfo/NVPTX/dbg-declare-alloca.ll		diff \| blob \| history
llvm/test/DebugInfo/X86/dbg-addr.ll		diff \| blob \| history
llvm/test/DebugInfo/X86/dbg-declare-alloca.ll		diff \| blob \| history
llvm/test/DebugInfo/X86/sret.ll		diff \| blob \| history
llvm/test/DebugInfo/assignment-tracking/X86/nested-loop-frags.ll		diff \| blob \| history

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