projects / platform / upstream / llvm.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 7afaa00) | patch
[SelectionDAG] ComputeNumSignBits add getValidMinimumShiftAmountConstant() ISD::SRA...
authorSimon Pilgrim <llvm-dev@redking.me.uk>
Mon, 13 Jan 2020 16:30:09 +0000 (16:30 +0000)
committerSimon Pilgrim <llvm-dev@redking.me.uk>
Mon, 13 Jan 2020 16:55:02 +0000 (16:55 +0000)
commit38e2c01221a9751c0b797417747200d2e9513b9f
tree1a05964472f8be632189653e90f06ebc69884532tree | snapshot
parent7afaa0099b907842b281c25c2a57937a2c307d3bcommit | diff
[SelectionDAG] ComputeNumSignBits add getValidMinimumShiftAmountConstant() ISD::SRA support

Allows us to handle more non-uniform SRA sign bits cases
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp diff | blob | history
llvm/test/CodeGen/X86/known-signbits-vector.ll diff | blob | history
Domain: System / Toolchain;