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(parent: ffa9916) | patch
dt-bindings: clock: Add StarFive JH7110 System-Top-Group clock and reset generator
authorXingyu Wu <xingyu.wu@starfivetech.com>
Tue, 14 Mar 2023 12:43:54 +0000 (20:43 +0800)
committerJaehoon Chung <jh80.chung@samsung.com>
Mon, 24 Jul 2023 23:24:34 +0000 (08:24 +0900)
commit38ce8db7bdc598ff5e0a6c66775a5ed1191ce99b
treeb22ca74c1298ba719bace4e5ed54c27ba04e9500tree | snapshot
parentffa9916d9e02b8de9c39e0aaf5cd1764f10076a2commit | diff
dt-bindings: clock: Add StarFive JH7110 System-Top-Group clock and reset generator

Add bindings for the System-Top-Group clock and reset generator (STGCRG)
on the JH7110 RISC-V SoC by StarFive Ltd.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Documentation/devicetree/bindings/clock/starfive,jh7110-stgcrg.yaml [new file with mode: 0644] blob
include/dt-bindings/clock/starfive,jh7110-crg.h diff | blob | history
include/dt-bindings/reset/starfive,jh7110-crg.h diff | blob | history
Domain: System / Kernel;