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(parent: 21534fe) | patch
clk: ingenic: Don't use CLK_SET_RATE_GATE for PLL
authorPaul Cercueil <paul@crapouillou.net>
Thu, 3 Sep 2020 01:50:46 +0000 (03:50 +0200)
committerStephen Boyd <sboyd@kernel.org>
Wed, 14 Oct 2020 03:04:50 +0000 (20:04 -0700)
commit3860dc599b7d3de869d9d7e2274d2ca8f1e2be86
treeedf46c7e0b793b0d54983244794d7f6541c50bdbtree | snapshot
parent21534fe39c494913849f3c46e41282b96bce7df6commit | diff
clk: ingenic: Don't use CLK_SET_RATE_GATE for PLL

CLK_SET_RATE_GATE means that the clock must be gated when being
reclocked. This is not the case for the PLLs in Ingenic SoCs.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20200903015048.3091523-3-paul@crapouillou.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/ingenic/cgu.c diff | blob | history
Domain: System / Kernel;