New RISC-V port (#281)
authorStef O'Rear <sorear2@gmail.com>
Sun, 11 Mar 2018 12:55:15 +0000 (05:55 -0700)
committerAnthony Green <green@moxielogic.com>
Sun, 11 Mar 2018 12:55:15 +0000 (08:55 -0400)
commit3840d49aaa831d649b1597518a2903dfed0d57f3
treeda49ee49ae31cc6e44beeb59930e995c4ec00ebb
parentdca52b55bc2ac0213c20849d7e9e19fbc9202023
New RISC-V port (#281)

* Add RISC-V support

This patch adds support for the RISC-V architecture (https://riscv.org).

This patch has been tested using QEMU user-mode emulation and GCC 7.2.0
in the following configurations:

* -march=rv32imac -mabi=ilp32
* -march=rv32g -mabi=ilp32d
* -march=rv64imac -mabi=lp64
* -march=rv64g -mabi=lp64d

The ABI currently can be found at
https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md .

* Add RISC-V to README

* RISC-V: fix configure.host
Makefile.am
README
configure.host
include/ffi_common.h
src/riscv/ffi.c [new file with mode: 0644]
src/riscv/ffitarget.h [new file with mode: 0644]
src/riscv/sysv.S [new file with mode: 0644]