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author	Dmitry Preobrazhensky <dmitri.preobrazhenski@gmail.com>
	Tue, 13 Dec 2022 11:36:43 +0000 (14:36 +0300)
committer	Dmitry Preobrazhensky <dmitri.preobrazhenski@gmail.com>
	Tue, 13 Dec 2022 11:36:43 +0000 (14:36 +0300)
commit	37e6f84026217b95e25306a0fa02fe408cbf9dc8
tree	b2551204d78aaca8d8ea5169f1f069bd7dbb1765	tree \| snapshot
parent	b19c26747f4e76549d29573946f097851db14829	commit \| diff

[AMDGPU][GFX10][DOC][NFC] Update assembler syntax description

Summary of changes:
- Enable register tuples with 9, 10, 11 and 12 registers (https://reviews.llvm.org/D138205).
- Enable abs and neg modifiers for v_cndmask_b32_dpp (https://reviews.llvm.org/D135900).
- Enable literal operands for permlane16/permlanex16 (https://reviews.llvm.org/D137332).
- Enable omod modifiers for v_max3_f16, v_min3_f16, etc. (https://reviews.llvm.org/D139469).
- Correct v_mov_b32_sdwa (it does not support abs and neg input modifiers yet).
- Enable tfe modifier for MUBUF loads (https://reviews.llvm.org/D137783).
- Enable image_gather4h (https://reviews.llvm.org/D130764).
- Minor corrections and improvements.

36 files changed:

llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst		diff \| blob \| history
llvm/docs/AMDGPU/gfx10_fx_operand.rst		diff \| blob \| history
llvm/docs/AMDGPU/gfx10_hwreg.rst		diff \| blob \| history
llvm/docs/AMDGPU/gfx10_imm16_0533c2.rst	[moved from llvm/docs/AMDGPU/gfx10_imm16_a04fb3.rst with 83% similarity]	diff \| blob \| history
llvm/docs/AMDGPU/gfx10_imm16_169952.rst	[moved from llvm/docs/AMDGPU/gfx10_imm16_73139a.rst with 84% similarity]	diff \| blob \| history
llvm/docs/AMDGPU/gfx10_label.rst		diff \| blob \| history
llvm/docs/AMDGPU/gfx10_m_28b494.rst	[moved from llvm/docs/AMDGPU/gfx10_m_254bcb.rst with 69% similarity]	diff \| blob \| history
llvm/docs/AMDGPU/gfx10_m_c141fc.rst	[moved from llvm/docs/AMDGPU/gfx10_m_f5d306.rst with 78% similarity]	diff \| blob \| history
llvm/docs/AMDGPU/gfx10_msg.rst		diff \| blob \| history
llvm/docs/AMDGPU/gfx10_sbase_b0aa25.rst	[moved from llvm/docs/AMDGPU/gfx10_sbase_010ce0.rst with 83% similarity]	diff \| blob \| history
llvm/docs/AMDGPU/gfx10_sdata_5e9fb5.rst	[moved from llvm/docs/AMDGPU/gfx10_sdata_3d2ab7.rst with 85% similarity]	diff \| blob \| history
llvm/docs/AMDGPU/gfx10_sdata_90678d.rst	[moved from llvm/docs/AMDGPU/gfx10_sdata_7e874d.rst with 85% similarity]	diff \| blob \| history
llvm/docs/AMDGPU/gfx10_sdata_c1aec6.rst	[moved from llvm/docs/AMDGPU/gfx10_sdata_c6aec1.rst with 84% similarity]	diff \| blob \| history
llvm/docs/AMDGPU/gfx10_soffset_0f304c.rst	[moved from llvm/docs/AMDGPU/gfx10_soffset_d01a5c.rst with 82% similarity]	diff \| blob \| history
llvm/docs/AMDGPU/gfx10_srsrc_80eef6.rst	[moved from llvm/docs/AMDGPU/gfx10_srsrc_e73d16.rst with 74% similarity]	diff \| blob \| history
llvm/docs/AMDGPU/gfx10_ssrc_bb715c.rst	[moved from llvm/docs/AMDGPU/gfx10_ssrc_9a4448.rst with 83% similarity]	diff \| blob \| history
llvm/docs/AMDGPU/gfx10_tgt.rst		diff \| blob \| history
llvm/docs/AMDGPU/gfx10_type_deviation.rst		diff \| blob \| history
llvm/docs/AMDGPU/gfx10_vaddr_a5639c.rst	[moved from llvm/docs/AMDGPU/gfx10_vaddr_cdc744.rst with 55% similarity]	diff \| blob \| history
llvm/docs/AMDGPU/gfx10_vdata_21b58d.rst	[moved from llvm/docs/AMDGPU/gfx10_vdata_15d255.rst with 81% similarity]	diff \| blob \| history
llvm/docs/AMDGPU/gfx10_vdata_2d6239.rst	[moved from llvm/docs/AMDGPU/gfx10_vdata_890652.rst with 83% similarity]	diff \| blob \| history
llvm/docs/AMDGPU/gfx10_vdata_4b260e.rst	[moved from llvm/docs/AMDGPU/gfx10_vdata_16d321.rst with 83% similarity]	diff \| blob \| history
llvm/docs/AMDGPU/gfx10_vdata_84fab6.rst	[moved from llvm/docs/AMDGPU/gfx10_vdata_a9ff5a.rst with 84% similarity]	diff \| blob \| history
llvm/docs/AMDGPU/gfx10_vdata_aa5a53.rst	[moved from llvm/docs/AMDGPU/gfx10_vdata_35851e.rst with 84% similarity]	diff \| blob \| history
llvm/docs/AMDGPU/gfx10_vdata_ad559c.rst	[moved from llvm/docs/AMDGPU/gfx10_vdata_0aba12.rst with 83% similarity]	diff \| blob \| history
llvm/docs/AMDGPU/gfx10_vdst_5d50a1.rst	[moved from llvm/docs/AMDGPU/gfx10_vdst_322561.rst with 71% similarity]	diff \| blob \| history
llvm/docs/AMDGPU/gfx10_vdst_5ec176.rst	[moved from llvm/docs/AMDGPU/gfx10_vdst_2ea017.rst with 77% similarity]	diff \| blob \| history
llvm/docs/AMDGPU/gfx10_vdst_875645.rst	[new file with mode: 0644]	blob
llvm/docs/AMDGPU/gfx10_vdst_a49b76.rst	[new file with mode: 0644]	blob
llvm/docs/AMDGPU/gfx10_vdst_d7c57e.rst	[new file with mode: 0644]	blob
llvm/docs/AMDGPU/gfx10_vdst_dfa6da.rst	[moved from llvm/docs/AMDGPU/gfx10_vdst_3d7dcf.rst with 87% similarity]	diff \| blob \| history
llvm/docs/AMDGPU/gfx10_vdst_eae4c8.rst	[moved from llvm/docs/AMDGPU/gfx10_vdst_473a69.rst with 78% similarity]	diff \| blob \| history
llvm/docs/AMDGPU/gfx10_vdst_f47754.rst	[new file with mode: 0644]	blob
llvm/docs/AMDGPU/gfx10_vsrc_ba3116.rst	[moved from llvm/docs/AMDGPU/gfx10_vsrc_533a4e.rst with 79% similarity]	diff \| blob \| history
llvm/docs/AMDGPU/gfx10_waitcnt.rst		diff \| blob \| history
llvm/docs/AMDGPU/gfx10_waitcnt_depctr.rst		diff \| blob \| history

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