Improve addressing of TI/TFmode
authorWilco Dijkstra <wdijkstr@arm.com>
Thu, 26 Oct 2017 16:34:03 +0000 (16:34 +0000)
committerWilco Dijkstra <wilco@gcc.gnu.org>
Thu, 26 Oct 2017 16:34:03 +0000 (16:34 +0000)
commit37e4d57b99efe65710bb4a000093c596ab3f5124
treec50f11ebc27468dce659470f8cae33c57099bdf4
parent9eaf97d6d7f1511638fb9209b7acf30e8f26a060
Improve addressing of TI/TFmode

In https://gcc.gnu.org/ml/gcc-patches/2017-06/msg01125.html Jiong
pointed out some addressing inefficiencies due to a recent change in
regcprop (https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00775.html).

This patch improves aarch64_legitimize_address_displacement to split
unaligned offsets of TImode and TFmode accesses.  The resulting code
is better and no longer relies on the original regcprop optimization.

For the test we now produce:

add x1, sp, 4
stp xzr, xzr, [x1, 24]

rather than:

        mov     x1, sp
        add     x1, x1, 28
        stp     xzr, xzr, [x1]

    gcc/
* config/aarch64/aarch64.c (aarch64_legitimize_address_displacement):
Improve unaligned TImode/TFmode base/offset split.

    testsuite/
* gcc.target/aarch64/ldp_stp_unaligned_2.c: New file.

From-SVN: r254111
gcc/ChangeLog
gcc/config/aarch64/aarch64.c
gcc/testsuite/ChangeLog
gcc/testsuite/gcc.target/aarch64/ldp_stp_unaligned_2.c [new file with mode: 0644]