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author	Alexander Timofeev <Alexander.Timofeev@amd.com>
	Thu, 6 Jun 2019 21:13:02 +0000 (21:13 +0000)
committer	Alexander Timofeev <Alexander.Timofeev@amd.com>
	Thu, 6 Jun 2019 21:13:02 +0000 (21:13 +0000)
commit	37bd9bd13750a368c0468f0768f29edc37dc540a
tree	a1389c1689b8a5bd10f976aa66e541bb47ea255f	tree \| snapshot
parent	169fc2b0209d5574fca0927a707706ea2d5f5a09	commit \| diff

[AMDGPU] Partial revert for the ba447bae7448435c9986eece0811da1423972fdd

   "Divergence driven ISel. Assign register class for cross block values
       according to the divergence."
       that discovered the design flaw leading to several issues that
       required to be solved before.

       This change reverts AMDGPU specific changes and keeps common part
       unaffected.

llvm-svn: 362749

37 files changed:

llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp		diff \| blob \| history
llvm/lib/Target/AMDGPU/SIISelLowering.cpp		diff \| blob \| history
llvm/lib/Target/AMDGPU/SIISelLowering.h		diff \| blob \| history
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/atomicrmw-nand.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/branch-relaxation.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/branch-uniformity.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/commute-shifts.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/extract_subvector_vec4_vec3.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/fabs.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/fdiv32-to-rcp-folding.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/fmin_legacy.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/fneg-fabs.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/fsub.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/i1-copy-from-loop.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/i1-copy-phi-uniform-branch.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.scale.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmed3.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mqsad.pk.u16.u8.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.qsad.pk.u16.u8.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/loop_break.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/madak.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/multilevel-break.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/select-opt.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/smrd.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/uniform-loop-inside-nonuniform.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/use-sgpr-multiple-times.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/valu-i1.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot-compute.ll		diff \| blob \| history

Domain: System / Toolchain;

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