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author	Shengchen Kan <shengchen.kan@intel.com>
	Wed, 16 Mar 2022 12:21:25 +0000 (20:21 +0800)
committer	Shengchen Kan <shengchen.kan@intel.com>
	Wed, 16 Mar 2022 12:25:42 +0000 (20:25 +0800)
commit	37b378386eefab39ef570db6172a8b8e660d7bfb
tree	2ea96dcb5e41e7dacc690037142c475f4d77c7b9	tree \| snapshot
parent	14d1a582093951973a5b94e4aab4d91ef4a0b80d	commit \| diff

[NFC][CodeGen] Rename some functions in MachineInstr.h and remove duplicated comments

70 files changed:

llvm/include/llvm/CodeGen/MachineInstr.h		diff \| blob \| history
llvm/lib/CodeGen/EarlyIfConversion.cpp		diff \| blob \| history
llvm/lib/CodeGen/ExpandPostRAPseudos.cpp		diff \| blob \| history
llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp		diff \| blob \| history
llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp		diff \| blob \| history
llvm/lib/CodeGen/InlineSpiller.cpp		diff \| blob \| history
llvm/lib/CodeGen/LiveRangeEdit.cpp		diff \| blob \| history
llvm/lib/CodeGen/MachineBasicBlock.cpp		diff \| blob \| history
llvm/lib/CodeGen/MachineInstr.cpp		diff \| blob \| history
llvm/lib/CodeGen/MachineLoopUtils.cpp		diff \| blob \| history
llvm/lib/CodeGen/MachineVerifier.cpp		diff \| blob \| history
llvm/lib/CodeGen/ModuloSchedule.cpp		diff \| blob \| history
llvm/lib/CodeGen/PeepholeOptimizer.cpp		diff \| blob \| history
llvm/lib/CodeGen/ProcessImplicitDefs.cpp		diff \| blob \| history
llvm/lib/CodeGen/RegisterCoalescer.cpp		diff \| blob \| history
llvm/lib/CodeGen/TailDuplicator.cpp		diff \| blob \| history
llvm/lib/CodeGen/TwoAddressInstructionPass.cpp		diff \| blob \| history
llvm/lib/CodeGen/UnreachableBlockElim.cpp		diff \| blob \| history
llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp		diff \| blob \| history
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp		diff \| blob \| history
llvm/lib/Target/AArch64/AArch64SLSHardening.cpp		diff \| blob \| history
llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp		diff \| blob \| history
llvm/lib/Target/AArch64/GISel/AArch64PostSelectOptimize.cpp		diff \| blob \| history
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp		diff \| blob \| history
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp		diff \| blob \| history
llvm/lib/Target/AMDGPU/SIFoldOperands.cpp		diff \| blob \| history
llvm/lib/Target/AMDGPU/SIISelLowering.cpp		diff \| blob \| history
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp		diff \| blob \| history
llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp		diff \| blob \| history
llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp		diff \| blob \| history
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp		diff \| blob \| history
llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp		diff \| blob \| history
llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp		diff \| blob \| history
llvm/lib/Target/ARC/ARCOptAddrMode.cpp		diff \| blob \| history
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp		diff \| blob \| history
llvm/lib/Target/ARM/ARMISelLowering.cpp		diff \| blob \| history
llvm/lib/Target/ARM/ARMInstructionSelector.cpp		diff \| blob \| history
llvm/lib/Target/ARM/ARMSLSHardening.cpp		diff \| blob \| history
llvm/lib/Target/ARM/Thumb2InstrInfo.cpp		diff \| blob \| history
llvm/lib/Target/ARM/ThumbRegisterInfo.cpp		diff \| blob \| history
llvm/lib/Target/AVR/AVRRegisterInfo.cpp		diff \| blob \| history
llvm/lib/Target/CSKY/CSKYRegisterInfo.cpp		diff \| blob \| history
llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp		diff \| blob \| history
llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp		diff \| blob \| history
llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp		diff \| blob \| history
llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp		diff \| blob \| history
llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp		diff \| blob \| history
llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp		diff \| blob \| history
llvm/lib/Target/Hexagon/HexagonPeephole.cpp		diff \| blob \| history
llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp		diff \| blob \| history
llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp		diff \| blob \| history
llvm/lib/Target/Mips/MipsBranchExpansion.cpp		diff \| blob \| history
llvm/lib/Target/Mips/MipsConstantIslandPass.cpp		diff \| blob \| history
llvm/lib/Target/Mips/MipsInstrInfo.cpp		diff \| blob \| history
llvm/lib/Target/Mips/MipsOptimizePICCall.cpp		diff \| blob \| history
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp		diff \| blob \| history
llvm/lib/Target/PowerPC/PPCMIPeephole.cpp		diff \| blob \| history
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp		diff \| blob \| history
llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp		diff \| blob \| history
llvm/lib/Target/SystemZ/SystemZElimCompare.cpp		diff \| blob \| history
llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp		diff \| blob \| history
llvm/lib/Target/SystemZ/SystemZShortenInst.cpp		diff \| blob \| history
llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp		diff \| blob \| history
llvm/lib/Target/WebAssembly/WebAssemblyFixBrTableDefaults.cpp		diff \| blob \| history
llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp		diff \| blob \| history
llvm/lib/Target/X86/X86ExpandPseudo.cpp		diff \| blob \| history
llvm/lib/Target/X86/X86FloatingPoint.cpp		diff \| blob \| history
llvm/lib/Target/X86/X86InstrInfo.cpp		diff \| blob \| history
llvm/lib/Target/X86/X86InstructionSelector.cpp		diff \| blob \| history
llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp		diff \| blob \| history

Domain: System / Toolchain;

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