drm/i915/icl: Add register definitions for Multi Segmented gamma
authorUma Shankar <uma.shankar@intel.com>
Wed, 12 Jun 2019 06:44:58 +0000 (12:14 +0530)
committerMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
Mon, 17 Jun 2019 08:26:47 +0000 (10:26 +0200)
commit377c70edd486754020ac4375ab2c403ed5108907
tree7e99f62c96f3282c1e97b2efdedc5bcb11db0ac9
parent89a72304f2f3d4baf14e71c570ea4d99a00dae07
drm/i915/icl: Add register definitions for Multi Segmented gamma

Add macros to define multi segmented gamma registers

V2: Addressed Ville's comments:
     Add gen-lable before bit definition
    Addressed Jani's comment
- Use REG_GENMASK() and REG_BIT()
V3: Addressed Ville's comments:
    - Put comments at the end of line.
    - Change the comment at start of ICL multisegmented gamma registers.
    Added Ville's r-b

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1560321900-18318-3-git-send-email-uma.shankar@intel.com
drivers/gpu/drm/i915/i915_reg.h