[X86][AMX] Replace PXOR instruction with SET0 in AMX pre config.
authorLuo, Yuanke <yuanke.luo@intel.com>
Wed, 4 May 2022 04:39:45 +0000 (12:39 +0800)
committerLuo, Yuanke <yuanke.luo@intel.com>
Thu, 5 May 2022 02:44:57 +0000 (10:44 +0800)
commit373ce147602cb2007ac861bc1956c16f473780a6
tree1ee4304b6558ce3972d0efad5c3e68ffb7acaa75
parentdc66897d4cd54749725e4cc189a88933fe3593b1
[X86][AMX] Replace PXOR instruction with SET0 in AMX pre config.

To generate zero value, the PXOR instruction need 3 operands that is
tied to the same vreg. If is not good in SSA form and with undef value
two address instruction pass may convert
`%0:vr128 = PXORrr undef %0, undef %0`
to `%1:vr128 = PXORrr undef %1:vr128(tied-def 0), undef %0:vr128`.
It is not expected.
It can be simplified to SET0 instruction which only take 1 destination
operand. It should be more friendly to two address instruction pass and
register allocation pass.
`%0:vr128 = V_SET0`
Also add AVX1 code path so that it is consistant to other code.

Differential Revision: https://reviews.llvm.org/D124903
llvm/lib/Target/X86/X86PreTileConfig.cpp
llvm/test/CodeGen/X86/AMX/amx-across-func.ll
llvm/test/CodeGen/X86/AMX/amx-config.ll
llvm/test/CodeGen/X86/AMX/amx-intrinsic-chain.ll
llvm/test/CodeGen/X86/AMX/amx-ldtilecfg-insert.ll
llvm/test/CodeGen/X86/AMX/amx-lower-tile-copy.ll
llvm/test/CodeGen/X86/AMX/amx-spill-merge.ll
llvm/test/CodeGen/X86/AMX/amx-spill.ll
llvm/test/CodeGen/X86/AMX/amx-tile-basic.ll