[TableGen] More named sub-operands work.
authorJames Y Knight <jyknight@google.com>
Tue, 8 Nov 2022 22:11:04 +0000 (17:11 -0500)
committerJames Y Knight <jyknight@google.com>
Wed, 7 Dec 2022 19:37:08 +0000 (14:37 -0500)
commit372240dfe3d5a933d9585663e15c4b6173ff23c8
treee35f5c344bcf8f3d9ee4696df3e26c5ad6bfe19f
parentb12fe0d429aa369665decd4f32175c63b542a4a1
[TableGen] More named sub-operands work.

Commit a538d1f13a13 first added support for named sub-operands in
CodeEmitterGen. We now add a few more features to that, enabling
further target cleanups.

1. Adds support for handling an EncoderMethod in a sub-operand in
CodeEmitterGen. Previously, the specified encoder of a sub-operand was
ignored, and only the default used.

2. Adds support for sub-operands in DecoderEmitter, along with support
for tied sub-operands.

The changes to the decoder required a few minor tweaks to a few
targets, where existing brokeness was exposed. In order to keep this
patch small, I left FIXMEs which will be addressed in upcoming
patches. (Except MIPS16, since its object file emission/decoding is
totally broken).

Differential Revision: https://reviews.llvm.org/D137653
16 files changed:
llvm/lib/Target/ARC/ARCISelDAGToDAG.cpp
llvm/lib/Target/ARC/ARCInstrFormats.td
llvm/lib/Target/ARC/ARCInstrInfo.td
llvm/lib/Target/ARM/ARMInstrFormats.td
llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
llvm/lib/Target/Mips/Mips16InstrInfo.td
llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
llvm/lib/Target/Sparc/SparcInstrInfo.td
llvm/test/TableGen/FixedLenDecoderEmitter/MultiOps.td [new file with mode: 0644]
llvm/test/TableGen/RegisterEncoder.td
llvm/utils/TableGen/CodeEmitterGen.cpp
llvm/utils/TableGen/CodeGenInstruction.cpp
llvm/utils/TableGen/CodeGenInstruction.h
llvm/utils/TableGen/DecoderEmitter.cpp
llvm/utils/TableGen/VarLenCodeEmitterGen.cpp