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(parent: 07a55f2) | patch
AMDGPU/GlobalISel: Legality/regbankselect for atomicrmw/atomic_cmpxchg
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Thu, 20 Dec 2018 00:33:49 +0000 (00:33 +0000)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Thu, 20 Dec 2018 00:33:49 +0000 (00:33 +0000)
commit36d4092173179b25b931a522361cf6139a7c635a
tree569bb8e8c0768af1e82a3a30692e2ff34dddbacftree | snapshot
parent07a55f27dc427df06c5354912d4053e21c84f9efcommit | diff
AMDGPU/GlobalISel: Legality/regbankselect for atomicrmw/atomic_cmpxchg

llvm-svn: 349708
27 files changed:
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp diff | blob | history
llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp diff | blob | history
llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomic-cmpxchg.mir [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-add.mir [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-and.mir [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-max.mir [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-min.mir [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-nand.mir [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-or.mir [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-sub.mir [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-umax.mir [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-umin.mir [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xchg-flat.mir [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xchg.mir [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xor.mir [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomic-cmpxchg.mir [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add.mir [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-and.mir [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-max.mir [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-min.mir [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-or.mir [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-sub.mir [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umax.mir [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umin.mir [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xchg.mir [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xor.mir [new file with mode: 0644] blob
Domain: System / Toolchain;